Emerging multiple-patterning high-density techniques require increased precision in evaluating the multi-layered patterns formed on a wafer. By way of non-limiting example, such techniques include self-aligned double patterning (SADP), double-exposure double patterning, and the like, used for creating high-density arrays of parallel lines as, for example, in the case of 32 nm and 22 nm flash memory structures.
The evaluation of such patterns may be provided by means of CD metrology, which may include recognition of structural elements, measuring, calibration, inspection, analyses, reporting, and/or other procedures necessary for assessing dimensions, sidewalls shape, line edge roughness, and/or other characteristics of patterns and structural elements thereof. The obtained results may be used for evaluating parameters and/or conditions of respective stages of manufacturing processes and providing necessary feedback.
CD metrology may be provided with the help of a variety of tools based on non-destructive observations as, by way of non-limiting example, scanning microscopes, atomic force microscopes, optical inspection tools, and others.
The problems of CD metrology for high-density manufacturing processes have been recognized in the Prior Art and various systems have been developed to provide solutions, for example:
US Patent Application No. 2010/009470 (Davis et al.) discloses an apparatus for adaptive self-aligned dual patterning and a method thereof. The method includes providing a substrate to a processing platform configured to perform an etch process and a deposition process and a metrology unit configured for in-vacuo CD measurement. The in-vacuo CD measurement is utilized for feedforward adaptive control of the process sequence processing platform or for feedback and feedforward adaptive control of chamber process parameters. In one aspect, a first layer of a multi-layered masking stack is etched to form a template mask, an in-vacuo CD measurement of the template mask is made, and a spacer is formed, adjacent to the template mask, to a width that is dependent on the CD measurement of the template mask.
US Patent Application 2009/142926 (Dai et al.) discloses several embodiments related to lithographic processes and used for improving line edge roughness (LER) and reduced CDs for lines and/or trenches. Embodiments use the combinations of polarized light lithography, shrink coating processes, and double exposure processes to produce synergetic effects in the formation of trench structures having good resolution, reduced CDs, reduced pitch, and reduced LER in the lines and/or trenches of the patterned interconnect structures. The embodiments may further include measuring the CDs and/or the LER prior to a second application of a shrink coating.
US Patent Application No. 2008/169862A (Park et al.) discloses a method for controlling patterns formed by a double patterning process including control of characteristics controlled responsive to CDs of the patterns. The method includes controlling two or more patterns having different CDs to optimally operate the patterns. The patterns may be individually controlled by signals provided to the patterns on the basis of the pattern's CDs. The signals may be controlled by controlling the magnitudes or the application time of the signals provided to the respective patterns.
US Patent Application No. 2007/105243 (Nagatomo et al.) discloses a method and apparatus for estimation of cross-sectional shape of a pattern. In an exposure process or etching process, an image feature amount, useful for estimating a cross-sectional shape of a target evaluation pattern, process conditions for the pattern, or device characteristics of the pattern, is calculated from an SEM image. The image feature amount is compared with learning data that correlates data preliminarily stored in a database, which includes cross-sectional shapes of patterns, process conditions for the patterns, or device characteristics of the patterns, to the image feature amount calculated from the SEM image. Thereby, the cross-sectional shape of the target evaluation pattern, the process conditions of the pattern, or the device characteristics of the pattern, are nondestructively calculated.
US Patent Application No. 2004/040930 (Tanaka et al.) discloses a method for quantitatively evaluating a three-dimensional shape of an etched pattern. Variations in signal amounts of an SEM image are utilized to compute three-dimensional shape data on the pattern associated with the etching process steps. Further provided is determination of etching process conditions and process control, based on obtained three-dimensional shape data.